2018
February Thursday 22

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2018 JAN REVIEW

Arduino Open Source Community member - Tier 1 Full Stack Developer

Arduino RISC?

2018 JAN | by Gene Casanova

Senior Systems Engineer


RISC Architecture

RISC stands for Reduced Instruction Set Computer; a type of microprocessor architecture utilizing a small, highly-optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures.

The first RISC projects came from IBM, Stanford, and UC-Berkeley in the late 1970s and early 1980s.  The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were all designed with a similar philosophy which has become known as RISC. Certain design features have been characteristic of most RISC processors:

  1. One cycle execution time: RISC processors have a CPI (clock per instruction) of one cycle. This is due to the optimization of each instruction on the CPU and a technique called pipelining.
  2. Pipelining: a techique enabling for simultaneous execution of parts, or stages, of instructions to more efficiently process instructions.
  3. Large number of registers: the RISC design philosophy generally incorporates a larger number of registers to prevent in large amounts of interactions with memory.

RISC processors only use simple instructions executable within one clock cycle.  The "MULT" command, could be divided into three separate commands: "LOAD," which moves data from the memory bank to a register, "PROD," which finds the product of two operands located within the registers, and "STORE," which moves data from a register to the memory banks.  A programmer would need to write four lines of assembly language processes:

LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3, A

The RISC strategy enables some very important advantages.  Because each instruction requires only one clock cycle to execute, the entire program will execute in approximately the same amount of time as the multi-cycle "MULT" command.  These RISC "reduced instructions" require less transistors of hardware space than the complex instructions, leaving more room for general purpose registers.  Because all of the instructions execute in a uniform amount of time (i.e. one clock), pipelining is possible.

Separating the "LOAD" and "STORE" instructions actually reduces the amount of work the computer must perform.  After a CISC-style "MULT" command is executed, the processor automatically erases the registers.  If one of the operands needs to be used for another computation, the processor must re-load the data from the memory bank into a register.  In RISC, the operand will remain in the register until another value is loaded in its place.

The Overall RISC Advantage 

Today, the Intel x86 is arguable the only chip which retains CISC architecture.  This is primarily due to advancements in other areas of computer technology.  The price of RAM has decreased dramatically.  In 1977, 1MB of DRAM cost about $5,000.  By 1994, the same amount of memory cost only $6 (when adjusted for inflation). Compiler technology has also become more advanced, enabling RISC use of RAM and emphasis on software has become ideal.


Arduino Open Source Community member - Tier 1 Full Stack Developer

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Use The Technology Wisely & Keep It Simple

- Cheers!

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